1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated integrated circuit products, and, more specifically, to various methods of forming multiple N-type semiconductor devices above a substrate, wherein the NFET devices have different threshold voltage (Vt) levels.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If the voltage applied to the gate electrode is less than the threshold voltage (Vt) of the device, then there is no current flow through the device (ignoring undesirable leakage currents, which are hopefully relatively small). However, when the voltage applied to the gate electrode is equal to or exceeds the threshold voltage (Vt) of the device, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region. During the fabrication of complex integrated circuit products using, for instance, CMOS technology, millions of transistors, e.g., N-channel transistors (NFET) and/or P-channel transistors (PFET), are formed on a substrate including a crystalline semiconductor layer.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the past decades. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. Given that the gate length (the distance between the source and drain regions) on modern transistor devices may be approximately 20-50 nm, and that further scaling is anticipated in the future, device designers have employed a variety of techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use of metal gate electrode structures, the incorporation of work function metals in the gate electrode structure, etc. One particular technique that has been employed to increase the performance of transistor devices involves so-called stress memorization techniques (SMT) wherein certain types of stresses are induced in the channel region of the device. More specifically, SMT techniques are used to create a tensile stress in the channel region for N-type transistors (to increase electron mobility). Stress engineering techniques typically involve 1) forming a patterned mask layer that exposes N-type transistors but covers any P-type transistors; 2) performing an amorphization implant process on the source/drain regions of the exposed N-type transistors; 3) removing the patterned mask layer; 4) forming a thin layer of silicon dioxide on the N-type transistors and the P-type transistors; 5) forming a specifically made silicon nitride layer on the silicon dioxide layer; 6) performing a brief re-crystallization anneal process (e.g., 650° C. for about 10 minutes in a nitrogen ambient); and 7) in some cases, performing one or more etching steps to remove the silicon nitride layer and the thin layer of silicon dioxide. During the etching process that is performed to remove the silicon nitride layer, the thin silicon dioxide layer protects the substrate and the sidewall spacers formed adjacent the gate structures of the devices. The above-described techniques employed in forming a desired tensile stress in the channel region of a FET are well known to those skilled in the art. The volume of the amorphized regions of the substrate, i.e., the amorphous silicon, is larger than the volume of the original silicon material that was amorphized. During the re-crystallization anneal process, the amorphous silicon is re-crystallized. When silicon changes from amorphous silicon to crystalline silicon, the volume of material will shrink, thereby creating the desired stress in the channel region of the device. This shrinking process also creates so-called stacking faults in the source/drain regions of the device as well. During the re-crystallization anneal process, the relatively stiff silicon nitride layer serves as a “volume confiner” to prevent stress relaxation during the re-crystallization process.
As noted above, the threshold voltage (Vt) of a transistor is a very important design parameter that greatly impacts the performance capabilities of the transistor device. In modern integrated circuit products, it is frequently the case that the product will have a plurality of N-type transistors that have different threshold voltage levels depending upon the functions provided by the circuit containing such transistors. In general, for transistors employed in applications requiring higher performance capabilities, such as logic or micro-processor circuits, the NFET transistors are designed to have the lowest threshold voltage level (Vt lowest) (hereinafter “LVT devices”). While such LVT devices typically exhibit a desirable high drive current, they may also exhibit undesirably high levels of leakage current, which may degrade device performance, e.g., an undesirable increase in power consumption. In contrast to the LVT devices, such an integrated circuit product may also contain transistors designed for low-power consumption applications. Transistors in such applications typically have a higher threshold voltage (Vt highest) (hereinafter “HVT devices” than that of the LVT devices. Such HVT devices may be employed in applications such as mobile phones, PDAs or other applications that rely on battery power. While such HVT devices typically exhibit a desirable low leakage current, and thus low power consumption, they may also exhibit undesirably low drive currents, which may degrade device performance, e.g., an undesirable decrease in switching speed, which tends to slow down the overall performance of the integrated circuit product.
One technique that is employed to vary the threshold voltage of N-type transistor devices involves performing separate and different so-called threshold voltage adjusting ion implantation processes on the channel regions of the different devices with a P-type dopant material. In general, for N-type devices, the higher the doping of the channel region during the threshold voltage adjusting implant process, the higher will be the threshold voltage of the resulting transistor device. FIGS. 1A-1C depict an illustrative example of this prior art technique. FIG. 1A depicts an integrated circuit product 10 wherein two illustrative NFET devices 10A, 10B will be formed in and above a semiconductor substrate 12 in separate active regions defined by an isolation structure 13. FIG. 1A depicts the product 10 at the point of fabrication wherein a patterned masking layer 14, e.g., a patterned layer of photoresist material, has been formed above the substrate 12 using known photolithography tools and techniques. The masking layer 14 masks the region of the substrate 12 where the NFET 10B will be formed but exposes the region of the substrate 12 where the NFET 10A will be formed. Thereafter, a first threshold voltage adjusting ion implant process 16 is performed to form a first threshold voltage adjusting implant region 16A in the region of the substrate 12 where the NFET device 10A will be formed.
FIG. 1B depicts the product after several process operations have been performed. First, the masking layer 14 (see FIG. 1A) was removed, and a second patterned masking layer 18 was formed above the substrate 12 using known photolithography tools and techniques. The masking layer 18 masks the region of the substrate 12 where the NFET 10A will be formed, and the implant region 16A, but exposes the region of the substrate 12 where the NFET 10B will be formed. Thereafter, a second threshold voltage adjusting ion implant process 20 is performed to form a second threshold voltage adjusting implant region 20A in the region of the substrate 12 where the NFET device 10B will be formed. The dopant concentration levels in the regions 16A, 20A are different, thereby resulting in the finished devices 10A, 10B having different threshold voltage levels.
FIG. 1C depicts the product 10 after additional components of the finished transistor devices 10A, 10B have been formed. Each of the devices comprises a schematically depicted gate insulation layer 22A, a gate electrode 22B, sidewall spacers 22C and source/drain regions 22D. Each of the devices exhibit different threshold voltage levels due to the different doping levels uses in forming the implant regions 16A, 20A.
Another prior art technique that is employed to vary the threshold voltages of N-type devices involves forming the devices with gate insulation layers of different thicknesses. In general, all other things being equal, the thicker the gate insulation layer, the greater will be the threshold voltage of the device. FIGS. 2A-2C depict an illustrative example of this prior art technique. FIG. 2A depicts an integrated circuit product 30 wherein two illustrative NFET devices 30A, 30B will be formed in and above the semiconductor substrate 12 in separate active regions defined by the isolation structure 13. FIG. 2A depicts the product 10 at the point of fabrication wherein a single threshold voltage adjusting ion implant process 32 is performed to form threshold voltage adjusting implant regions 32A in the regions of the substrate 12 where both of the NFET devices 30A, 30B will be formed.
FIG. 2B depicts the product 30 after several process operation have been performed. First, a layer of gate insulation material 34 was formed on the substrate 12, e.g., silicon dioxide. In the drawings, the relative thickness of the gate insulation material 34 has been exaggerated for purposes of explanation. The layer of gate insulation material 34 has an original thickness 34A and it may be formed by either a deposition process, as depicted, or by a thermal growth process, wherein the layer 34 would not form on the isolation structure 13. After the layer of gate insulation material 34 was formed, a patterned masking layer 36 was formed above the layer of gate insulation material 34 using known photolithography tools and techniques. The masking layer 36 masks the region of the substrate 12 where the NFET 30A, with a thicker gate insulation layer, will be formed, but exposes the region of the substrate 12 where the NFET 10B, with a relatively thinner gate insulation layer, will be formed.
FIG. 2C depicts the product 30 after additional components of the finished transistor devices 30A, 30B have been formed. Each of the devices comprises a schematically depicted gate insulation layer 22A, a gate electrode 22B, sidewall spacers 22C and source/drain regions 22D. However, since the devices 30A, 30B have gate insulation layers 22A of different thickness, each of the devices 30A, 30B exhibit different threshold voltage levels.
As can be seen from the forgoing, each of the prior art techniques involves performing numerous masking and ion implantation processes, both of which are time-consuming and expensive process operations in the world of semiconductor manufacturing. The situation becomes even more problematic and complex when an integrated circuit product that is being manufactured requires devices with three or more different threshold voltage levels, as the above process steps must be increased, all of which increases the time and expense of fabricating such integrated circuit products.
In the case of an integrated circuit product that employs LVT devices and HVT devices, but does not employ any SMT techniques to improve the performance of the devices, two separate ion implantation masking layers are employed and two separate threshold voltage adjusting ion implantation processes are performed (each with different dopant doses) to achieve the desired threshold voltage levels for each of the devices. For example, a first implant mask is formed that exposes one of the device types while masking the other type of devices, and the first threshold voltage adjusting ion implant process is performed. This process is then repeated for the other devices. The dopant dose used in the threshold voltage adjusting ion implant process for the LVT devices is lower than the dopant dose used in the threshold voltage adjusting ion implant process for the HVT devices. This results in the LVT devices and HVT devices having threshold voltage implant regions with a lower dopant concentration, e.g., about 10e15-10e17 ions/cm3 (for the LVT devices) and about 10e17-10e19 ions/cm3 (for the HVT devices). In such an application, the performance of the integrated circuit product is not as great as it would have been when SMT techniques are used in combination with the threshold voltage adjusting implants to improve device performance.
Additional complexities arise when SMT techniques are also employed in an attempt to increase the performance level of N-type devices. For example, when SMT techniques and threshold voltage implant techniques are both employed on a product that employs LVT devices and HVT devices, an additional third masking layer is needed to expose all of the N-type devices for an amorphization implantation process as part of the SMT processing, while covering all of the P-type devices. The SMT approach, if combined with replacement gate architecture, desirably lowers the threshold voltage for each of the N-type devices by shifting the conduction band gap of the silicon channel region and by reducing the band gap energy level of the silicon channel material. Unfortunately, the use of the additional SMT technique also undesirably increases the junction leakage currents of the N-type devices due to the reduction of the band gap of the silicon channel material. The increased leakage current is particularly undesirable for the HVT devices, as it adversely impacts the ability of such a degraded HVT device to meet the low power consumption levels that are needed for products that use HVT devices.
The present disclosure is directed to various methods of forming multiple N-type semiconductor devices above a substrate, wherein the N-type devices have different threshold voltage levels, that may solve or reduce some of the problems mentioned above.